Fin-based field effect transistors (FINFETs) are vertical transistor devices in which a semiconductor fin is located on a substrate and is used to define the source, drain, and channel regions of the device. A gate overlies the fin in the channel area, and in some configurations multiple fins may be used to provide a multi-gate transistor architecture. The multiple gates may be controlled by a single gate, where the multiple gate surfaces act electrically as a single gate, or by independent gates.
FINFET devices may provide desired short channel control to enable technology scaling down to 10 nm nodes and beyond. With ever-increasing device integration densities, various challenges may arise with respect to the gate of FINFET semiconductor devices. For example, spurious nodules may form on a gate during the formation of raised source/drain regions.
A gate structure for a semiconductor FINFET device 20 includes a gate 22 comprising polysilicon formed above a gate dielectric layer 24, as illustrated in FIG. 1. To protect the gate 22 during formation of raised source/drain regions 32, a hard mask 26 is formed on an upper surface of the gate 22, and a pair of sidewall spacers 28 is formed on the sidewalls of the polysilicon layer. The pair of sidewall spacers 28 is intended to entirely cover the sidewall surfaces of the gate 22.
Any exposure of the gate 22 through either the hard mask 22 and/or the sidewall spacers 28 during the formation of raised source/drain regions 32 results in unwanted epitaxial growth of silicon nodules 40 on the upper surfaces of the gate where they are exposed. Plasma etching is typically used to form the gate 22. However, when the gate 22 is formed in an open or less dense area on the substrate 30, the plasma etching heats the gate differently as compared to being heated in a confined or more dense area. As a result, the gate 22 may have a tapered profile. Because of the tapered profile, the pair of sidewall spacers 28 may leave part of the gate 22 exposed. This exposure allows for the growth of the silicon nodules 40.
One approach to avoiding the formation of spurious nodules on a gate is disclosed in U.S. Pat. No. 7,700,425 to Wagner et al., which is hereby incorporated herein in its entirety by reference. In Wagner et al, an amorphous silicon cap layer is formed in the top surface of the gate, and a hard mask is formed on top of the cap layer. A notch is formed in the periphery of the cap layer between the gate and the hard mask. The notch is filled with a plug composed of a dielectric material. The plug extends down below the level of the top of the sidewall spacers for the purpose of eliminating exposure of the gate. Nonetheless, other approaches to eliminating the exposure of the gate during formation of raised source/drain regions may be desirable.